Implementation of FIR Filter for Low Power and Area Minimization Using Shift –Add Method without Multipliers
Authors: Sumalatha Madugula, Panchala Venkata Naganjaneyulu, Kodati Satya Prasad
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In VLSI design, performance parameters such as speed and hardware cost are important facts during the implementation of complex algorithms. In this paper, Low Cost Carry SeLect Adder Finite Impulse Response (LC-CSLA-FIR) is introduced to perform the FIR filter operations. With the help of shifter-I, shifter-II, and Shifter-III circuits, the FIR filter operation is performed without using any multipliers. In this new architecture, there is no need of storing the co-efficient in the ROM and number of multipliers. Due to the absence of multipliers, the quantity of hardware is reduced and the performance of the architecture is increase. With the help of Verilog code, the FIR filter architecture is verified in Modelsim software. After Field Programmable Gate Array (FPGA) analysis, Look Up Table (LUT), slices, flip flops, frequency and ASIC implementation area, power, delay, Area Power Product (APP), Area Delay Product (ADP) is improved in LC-CSLA-RFIR method compare to conventional methods.