International Journal of Intelligent Engineering and Systems

9

Authors: Yuto Takeda, Yasuo Musashi, Kenichi Sugitani, Toshiyuki Moriyama

We statistically investigated the total ANY resource record (RR) based DNS query request packet traffic from the Internet to the top domain DNS server in a university campus network from January 1st, 2011 to December 31st, 2012. The obtained results are: (1) we found a significant increase in the inbound ANY RR based DNS query request traffic at November 28th, 2011. (2) In the DNS query request packet traffic, we observed only a query keyword of the campus domain name. (3) We found a correlation between the total inbound DNS query request packet traffic and the DNS query request packet traffic including the query keyword. (4) We also carried out the loading test sending ANY, A, and PTR RRs based unique DNS queries to a test DNS server, however, we observed no difference among the vmstat parameters based on the queries, and the load value was only 0.10-0.20. These results indicate that the ANY RR based DNS request packet traffic is quite strange. Therefore, we should pay much attention to the ANY RR based DNS query request traffic including the single domain name.

9

Authors: J.Manjula, S.Malarvizhi

This paper presents a design and performance analysis of tunable RF front end circuits such as RF band pass filter and VCO for multiband applications. The tunable element is an active inductor, built by MOS transistors. It is attractive due to its tunable and larger inductance values. The RF band pass filter is realized using active inductor with suitable input and output buffer stages. The tuning of center frequency for multiband operation is achieved through the controllable current source of the active inductor. The tunable range of the band pass filter varies from 3.9 GHz to 12.3 GHz. The simulation results of band pass filter have minimum noise figure of 23 dB and has less power dissipation of 2.83mW. The simulated IIP3 is -9.6dBm for 1st and 3rd order frequency of 7.94 GHz and 7.93 GHz respectively. The VCO designed using active inductor has the tuning range of 0.384 GHz to 1.620 GHz with the phase noise of -139dBc/Hz at the offset of 1MHz. It consumes less power of 1.754mW with the figure of merit of 189dBc/Hz. The designed active inductor, RF band pass filter and VCO are simulated in 180nm CMOS process using Synopsys simulation tool.

9

Authors: M. Arun, S. Saravanan

At present, Boolean algebra based computations by the use of silicon based semiconductor technology are irreversible in nature. This is due to the mismatch of number of inputs and outputs. Reversible logic circuit maps unique input to the output and ensure one to one mapping and basis for emerging applications like low-power design, quantum computation, optical computing, bioinformatics and nanotechnologies. In computing paradigm, Arithmetic Logic Unit (ALU) is one of the computing intensive building blocks of the computer that performs arithmetic and logical operations. This work understands and nurtures the necessity of reversible ALU for future revolutionary computing technologies. In this paper, a 4x4 reversible gate which alone performs arithmetic and logic operations is proposed and compared with other reversible gates like TSG, HNG and MKG, in terms of quantum cost, I/O lines and Taffoli gates. The results of different synthesis methods of 4x4 ALG using Revkit tool are studied. Proposed gate performs better than existing methods and ensures maximum logical operations like full adder, full subtractor and all logical operations with less hardware cost where other existing gates are not viable.

9

Authors: Cao XiaoQiang, Zhang Jun, Xiong Xing

Nowadays, along with the development of technology of the high-speed Analog to Digital Converter (ADC) and Field Programmable Gate Array (FPGA), the design and the implementation of high-speed and highaccuracy data acquisition system is also becoming economic and feasible. In this paper, we designed a high-speed, high-precision, portable data acquisition and processing system in Altera Corporation cyclone II FPGA platform, and achieved the communication between the system and PC via USB2.0 interface. The whole system is divided into four parts: the A/D module, the FPGA module, the USB module and the LABVIEW (Laboratory Virtual Instrument Engineering Workbench) module. We used AD9467 as the core chip of the A/D module, and the characteristics and specific circuit design of AD9467 are explained in detail; the FPGA module is the core of the entire system, which is not only the center of the signal conditioning but also the control center to ensure the whole system to work in an orderly manner. We also introduced the concrete realization of the design of clock part, LVDS converter module and USB control module. The programming language used verilog hardware description language. And then we introduced the design of the USB module in detail where the Lab VIEW module was the module of human-computer interaction that introduced the concrete realization of the PC display software using G language. Finally, we debugged and tested the entire system, the results show that the design can work very well and meet the requirements of the system design.

10

Authors: Yuqing Song, Dongpeng Yue, Shaoqing Mo

In this paper we introduce a graph grammar based method to fuse the low level features and apply them to object detecting and tracking. In our algorithm, the graph grammar rules are used to detect the object in the beginning of the video sequence and then dynamically adjust the tracking procedure. Our tracking algorithm consists of two phases: key points tracking and tracking by graph grammar rules. The key points are computed by using salient level set components. All key points, as well as the colors and the tangent directions, are fed to a Kalman filter for object tracking. Then the graph grammar rules are used to dynamically examine and adjust the tracking procedure to make it robust. The effectiveness of the algorithm has been demonstrated by experiments.